1. Field of the Invention
Embodiments of the invention relate to a display device, and more particularly to a liquid crystal display device and a fabricating method thereof. Although embodiments of the invention are suitable for a wide scope of applications, it is particularly suitable for reducing the number of mask process and preventing an electric contact defect between a data pad and a data line.
2. Description of the Related Art
Generally, a liquid crystal display device controls light transmittance of liquid crystal molecules using an electric field, to thereby display a picture. More specifically, the electric field is provided between a pixel electrode and a common electrode arranged to be opposed to each other on upper and lower substrates of a liquid crystal display device. The lower and upper substrates are often respectively referred to as thin film transistor array substrate and color filter array substrate. A spacer maintains a cell gap, filled with liquid crystal molecules, between the two substrates. The thin film transistor array substrate includes a plurality of signal wirings, thin film transistors, and an alignment film coated thereon for aligning the liquid crystal molecules. The color filter array substrate includes a color filter for implementing a color, a black matrix for preventing light leakage, and an alignment film coated thereon for aligning the liquid crystal molecules.
Since the thin film transistor substrate in such a liquid crystal display device is fabricated by a semiconductor processing and requires a plurality of mask processes, the fabricating process is a major factor in the manufacturing cost of a liquid crystal display panel. For example, one mask process includes many processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection. To reduce complexity caused by many mask processes, manufacturers of liquid crystal display devices have put a lot of effort into researching manufacturing techniques that reduce the number of mask process. As a result, a thin film transistor substrate manufacturing process has been developed that reduces the number of mask process to three rounds.
FIG. 1 is a plan view showing a data pad portion of a thin film transistor array substrate using a related art three-round mask process, and FIG. 2 is a cross-sectional view of the data pad portion taken along line I-I′ in FIG. 1. Referring to FIG. 1 and FIG. 2, the data pad portion includes a data pad 30, and a data link portion 40 extending from a data line 4 to connect to the data pad 30. The data pad 30 is connected to output pins of a data driving integrated circuit in a one-to-one relationship to supply a data signal of the data driving integrated circuit to the data line 4. Such a data pad 30 includes a lower data pad electrode 32 and an upper data pad electrode 34. Herein, the upper data pad electrode 34 is connected, via a first contact hole 33 passing through a gate insulating film 36 and a protective film 52, to the lower data pad electrode 32.
The data link portion 40 electrically connects the data pad 30 to the data line 4. To this end, the data link portion 40 includes a lower data link electrode 42, an upper data link electrode 46, a link electrode 44. Herein, the lower data link electrode 42 is connected to the lower data pad electrode 32. The upper data link electrode 46 is connected to the data line 4. The link electrode 44 connects the lower data link electrode 42 exposed via a second contact hole 43 to the upper data link electrode 46 exposed via a second contact hole 43. Herein, the second contact hole 43 is positioned at a center of the data link portion 40 and passes through the protective film 52, the upper data link electrode 46, a semiconductor layer 38, and the gate insulating film 36 to expose the lower data link electrode 42.
FIG. 3A to FIG. 3E are cross-sectional views showing a method of fabricating the thin film transistor array substrate in FIG. 2. Referring to FIG. 3A, a first mask process disposes a gate metal layer on a substrate 2, and then a photolithography process and an etching process using a first mask provide a gate metal pattern group, including the lower data pad electrode 32 and the lower data link electrode 42, are carried out.
Referring to FIG. 3B, an insulating film, a semiconductor material active layer, an ohmic contact material and a metal layer are provided on the gate metal pattern group, including the lower data pad electrode 32 and the lower data link electrode 42. A second mask process, including a photolithography process and an etching process, uses a second mask to provide the semiconductor layer 38, including an active layer and an ohmic contact layer, and a source/drain metal pattern group 46, including a data line, on the gate insulating film 36 are carried out.
Next, referring to FIG. 3C, a protective film 52 is formed over the semiconductor layer 38, including an active layer and an ohmic contact layer, and a source/drain metal pattern group 46, including a data line. A third mask process forms a photo-resist pattern 60 by exposure and development processes using a third mask, and then the first contact hole 33 passing through the protective film 52 and the gate insulating film 36 to the lower data pad electrode 32 is formed by an etching process using the photo-resist pattern 60 while the second contact hole 43 is formed passing through the protective film 52, the upper data link electrode 46, the semiconductor layer 38 and the gate insulating film 36 to the lower data link electrode 42. A transparent conductive film 44a is provided over the photo-resist pattern 60 and into the first and second contact holes 33 and 43.
As shown in FIG. 3D, the photo-resist pattern with the transparent conductive layer 44a thereon is removed with a stripper during a lift-off process to provide a transparent electrode pattern group, including the link electrode 44 and the upper data pad electrode 34.
As described above, in the data link portion 40, thin films, including the protective film 52, a source/drain metal layer, the semiconductor layer 38 and the gate insulating film 36, should be etched using the third mask process to expose the lower data link electrode 42 via the second contact hole 43. The etching time for the first contact hole 33 may need to be reduced to prevent over-etching of the lower data pad electrode 32 in the first contact hole 33 so that just the protective film and the gate insulating film 36 are etched. However, a problem may occur when reducing etching time to prevent over-etching in that the gate insulating film 36 in the second contact hole 43 may not be entirely etched away, as shown in FIG. 3E. Thus, leaving leftover gate insulating film 36 on the lower data link electrode 42. Accordingly, the gate insulating film 36 is left between the lower data link electrode 42 and the upper data link electrode 46 to generate an electric contact defect between the lower data link electrode 42 and link electrode 44. As a result, a data signal of the data driving integrated circuit can not be supplied to the data line 4.